1. Field of the Invention
The present invention relates to a semiconductor device in which semiconductor integrated circuit sections are protected, electric connections of semiconductor elements to external equipment are ensured, external terminals are soldered to a resin substrate for BGAs, wafer-level chip-size packages, and so on, and a high degree of soldering reliability is ensured over an extended period of time, and a method for manufacturing the same.
2. Description of the Related Art
In recent years, electronic components such as semiconductors have been required to have higher packaging densities in order to meet improvements in performance and carryability of electronic gear. In addition, in response to the requirement, progress has been made in fabricating smaller and thinner semiconductor devices having more pins in spite of the same device size, which has brought about the development of BGAs and various CSPs (chip-size packages) having the pins arranged on their area.
In particular, WLCSPs (wafer-level CSPs), in which wiring for connections from semiconductor element electrodes to external terminals on semiconductor wafers is formed, and the wafers are divided in their final manufacturing process, have recently received attention as a technique by which extremely small-sized packages equivalent to bare chips are implemented (see Japanese Patent Laid-Open No. 54649/1999).
In the following, a conventional semiconductor device called “WLCSP” and a method for manufacturing the device will be described with reference to drawings.
FIG. 20 is a partially-opened perspective view showing a semiconductor device called “WLCSP”. In FIG. 20, reference numeral 1 denotes a semiconductor element, reference numeral 2 denotes a semiconductor element electrode, reference numeral 3 denotes a passivation film, reference numeral 4 denotes a insulating resin layer, reference numeral 7a denotes a metal wire, reference numeral 7b denotes a metal land, reference numeral 8 denotes a solder resist, and reference numeral 9 denotes an external terminal.
FIGS. 21 to 23 are sectional views showing a conventional method for manufacturing the semiconductor device by manufacturing process. In FIGS. 21 to 23, the same components as those shown in FIG. 20 are denoted by the same reference numerals, and their descriptions are omitted.
First a photosensitive resin is generally used as the insulating resin layer 4, and then applied onto the semiconductor element 1. Thereafter, the photosensitive resin is exposed using an aligner, a stepper, or the like. The photosensitive resin on the semiconductor element electrodes 2 and other portions where no photosensitive resin is required is developed and removed, after which the remaining photosensitive resin is cured to form the resin insulating layer 4 (see FIG. 21A).
In this case, since the semiconductor element electrodes 2 usually comprises Al and Si or Al, Si, and Cu, a weakly alkaline or organic developing solution is used as a developing solution for the photosensitive resin being a material used for forming the resin insulating layer 4 and as a material which does not melt the semiconductor element electrodes 2 during development.
An evaporated metal later 5 is formed on the entire surface of the semiconductor element 1 on which the resin insulating layer 4 is patterned by sputtering (see FIG. 21B). At this time, a metal barrier is first formed as the evaporated metal layer 5, and then, subsequently, a plating seed layer is formed under vacuum. Also, prior to sputtering, the surface of the resin insulating layer 4 is roughened finely by plasma treatment to improve the adhesion strength of the metal barrier to the resin insulating layer 4. It is essential only that methods used for plasma treatment and reactant gases be able to selectively etch the resin of the insulating resin layer 4 in relation to the etching of the semiconductor element electrodes 2 and the passivation film 3; in this case, RIE (Reactive Ion Etching) treatment and O2 gas, N2 gas, or a mixed gas of O2 gas and CF4 gas are used.
As to the metal barrier, a metal, such as Cr, is used which has a strong adhesion strength to the insulating resin layer 4, the semiconductor element electrodes 2, and the passivation film 3 and has barrier properties to the etchant for the plating seed layer. As the plating seed layer, it is necessary for the metal to exhibit a low resistivity during electroplating, so that Cu is generally used. The thickness of the metal barrier used is of the order of 0.1 to 0.2 μm in view of the barrier properties of the seed layer to the etchant, and the thickness of the plating seed layer used is of the order of 0.2 to 0.5 μm in view of electric resistance, deposition stress, and ease of etching. Then, a photosensitive resist material is applied onto the plating seed layer, after which a plating resist 6 is formed by drying, exposing, and developing the photosensitive resist material (see FIG. 21C). In general, the plating resist 6a is formed so as to have a thickness of the order of 8 to 15 μm in order that the thickness of copper-electroplating at a subsequent process may be of the order of 5 to 11 μm. Thereafter, the development residue of the plating resist 6a is removed by plasma treatment using 02 gas.
Then openings are made in the plating resist 6a by copper-electroplating, and a thick-film metal layer 7 is selectively formed on portions where the seed layer is exposed (see FIG. 22A). The thick-film metal layer 7 is formed so as to have a thickness of the order of 5 to 11 μm in view of its electric resistance and mechanical strength.
After the formation of the thick-film metal layer 7, the plating resist 6a is exfoliated. Further, the peel residue of the plating resist 6a is removed by plasma treatment using 02 plasma (see FIG. 22B).
Next, when the entire surface of the seed layer and the thick-film metal layer 7 is etched by a copper etchant, the copper of the seed layer which is thinner than the thick-film metal layer 7 is first removed. At this time, as to the etchant used for etching the seed layer, a solution is used which is capable of selectively etching the seed layer without melting the metal barrier. Then, the metal wires 7a having a desired pattern and the metal lands 7b are formed by etching the entire surface of the metal barrier (see FIG. 22C).
Next, a photosensitive resin is applied onto the resin insulating layer 4 and the thick-film metal layer 7, after which the resin is dried and exposed. Then the photosensitive resin on the metal lands 7b and other portions where no photosensitive resin is required is developed and removed, after which the remaining resin is cured to form the solder resist layer 8 (see FIG. 23A).
Thereafter, a solder paste is print-melted on the metal lands to form the external terminals 9 (see FIG. 23A). At this time, low-melting metal balls may be mount-melted to form the external terminals 9 instead of print-melting the solder paste. Also, Ni—Au plating may be carried out on the metal lands prior to the printing of the solder paste.
According to the conventional method, however, the copper layer, which forms the wires and the lands, is finely roughened as its surface treatment in order to enhance its adhesion to the solder resist, while its entire shape between the metal lands and the external terminals is flat. For this reason, when the external terminals undergo thermal stress resulting from mechanically-applied external force and a difference in their thermal expansions during the inspection process after assembly and packaging process of the semiconductor device and in the state that they are connected to external equipment after the packaging, cracks 13 may occur at the junction interfaces of the lands 7b and the external terminals 9 as shown in FIG. 24, and the disconnection of the external terminals occur on rare occasion. Even when the crack or disconnection does not occur at a single load, long-duration junction reliability may deteriorate due to the formation of the alloy layer at the interface under high temperature atmosphere. At a result, as shown in FIGS. 25A and 25B, there have been obtained a method for increasing junction strength resulting from metallic bond generated at the junction interface 14 of the land portion 7b and the external terminal 9 by increasing the area of the junction interface 14 of the land portions 7b and the external terminals 9. However, in case where the brittle metal layer resulting from metal diffusion is formed at the junction interface 14 by thermal hysteresis, the junction strength is extremely reduced, so that the improvement in the junction strength resulting from the increase in their junction area has not yet brought about a radical solution of the problems of the occurrence of cracks at the junction interface and the disconnection of external terminals.
In recent years, the influence of lead upon environment has become a worldwide problem, so that the conversion of conventional lead-containing Pd—Sn eutectic solder to solder containing no lead (hereinafter referred to as Pd-free solder) has been proceeding at various companies including those in the electric and parts industries. Since the melting point of Pd-free solder is higher than that of Pd—Sn eutectic solder, the set temperature of a reflow process becomes high, so that the metal diffusion has become prone to spread. In fact, the frequency of the occurrence of cracks at the junction interface and the falloff of external terminals has been further increased than in the past.